The use of high-speed buffer stores, often called "caches", for improving the operation of data processing systems is well established in the art. Several systems are known in which a plurality of caches are provided.
U.S. Pat. No. 4,141,067 to A. McLagan discloses a multiprocessor system in which each CPU has its own cache store. Separate latches are provided between each cache store and its CPU to buffer data. No transfer or interaction between the several caches is provided, as each cache serves its own processor.
In U.S. Pat. No. 4,144,566 to C. Timsit, a parallel processor is disclosed having a large number of elementary processors connected in parallel. Each elementary processor has its own normal storage unit and its own small capacity fast storage unit. These fast storage units are interconnected to allow the desired parallel processing. However, no transfer of separate data sets between the fast stores or between a selectable fast store and a single common main store are provided.
U.S. Pat. No. 4,228,503 to J. C. Waite et al. describes a multi-requestor system in which each requestor has its own dedicated cache store. Besides having access to its own cache store for obtaining data, each requestor also has access to all other dedicated cache stores for invalidating a particular data word therein if that same data word has been written by that requestor into its own dedicated cache store. However, a requestor cannot obtain data from another cache which is not its own, and no data transfers between caches are provided.
In U.S. Pat. No. 4,354,232 to C. P. Ryan a computer system is disclosed which has a high-speed cache storage unit. A particular buffer stage is provided between the cache and the main storage and CPU, for storing read and write data transfer commands and associated data. Though flexibility is gained in data transfer, a separate buffer unit and control logic are required solely for this purpose.
The article "Data processing system with second level cache" by F. Sparacio, IBM Technical Disclosure Bulletin, Vol. 21, No. 6, November 1978, pp. 2468-2469, outlines a data processing system having two processors and a two-level cache arrangement between each processor and the common main store. No disclosure is made of the internal organization of the cache stores and of the interconnecting busses and circuits.
An article by S. M. Desar "System cache for high performance processors" which was published in IBM Technical Disclosure Bulletin, Vol. 23, No. 7A, December 1980, pp. 2915-1917 presents a basic block diagram of a data processing system having plural processors each with its own dedicated cache store, and a common system cache in a separate level between the dedicated processor caches and main storage. Also in this article, no details are given on interconnecting busses and circuits and on the internal organization of the cache storage units.